How many NAND gates are used in an OR gate?
(A). Two
(B). Three
(C). Four
(D). Five
Answer
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Hint: You can start by explaining the basic construction of the combination of three NAND gates that behave as an OR gate. Remember to write the Boolean expression for the NAND gate and the OR gate. Then draw the truth table for the input and corresponding outputs of this combination and compare it to the truth table of an OR gate.
Complete step-by-step answer:
To make an OR gate from NAND gates we would have to use the combination of three NAND gates. The NAND gates are combined in the following manner to form an OR gate
The Boolean expression for an OR gate is $A + B$ and the Boolean expression for a NAND gate is $\overline {A \cdot B} $ .
The truth table for the following arrangement is given below.
Column A contains the input for the first NAND gate.
Column B contains the inputs for the second NAND gate.
Column C contains the output of the first NAND gate.
Column D contains the output of the second NAND gate.
Column E contains the output for the third and final NAND gate.
We know that the truth table of an OR is as follows.
Here, column A and B contain the initial inputs and column C contain the final output of the combinations.
The final outputs of the first and the second table are the same which confirms that the combination of NAND gates shown above collectively behaves like an OR gate.
Hence, option B is the correct choice.
Note: The process that we used in the solution above highlights a very important characteristic of logic gates. Logic gates can be used in various combinations to produce other logic gates, it might look inefficient to use three NAND gates to make a single OR gate but there are circumstances where this becomes a necessity and hence this implementation is used.
Complete step-by-step answer:
To make an OR gate from NAND gates we would have to use the combination of three NAND gates. The NAND gates are combined in the following manner to form an OR gate
The Boolean expression for an OR gate is $A + B$ and the Boolean expression for a NAND gate is $\overline {A \cdot B} $ .
The truth table for the following arrangement is given below.
Column A contains the input for the first NAND gate.
Column B contains the inputs for the second NAND gate.
Column C contains the output of the first NAND gate.
Column D contains the output of the second NAND gate.
Column E contains the output for the third and final NAND gate.
A | B | C | D | E |
0 | 0 | 1 | 1 | 0 |
0 | 1 | 1 | 0 | 1 |
1 | 0 | 0 | 1 | 1 |
1 | 1 | 0 | 0 | 1 |
We know that the truth table of an OR is as follows.
A | B | C |
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 1 |
Here, column A and B contain the initial inputs and column C contain the final output of the combinations.
The final outputs of the first and the second table are the same which confirms that the combination of NAND gates shown above collectively behaves like an OR gate.
Hence, option B is the correct choice.
Note: The process that we used in the solution above highlights a very important characteristic of logic gates. Logic gates can be used in various combinations to produce other logic gates, it might look inefficient to use three NAND gates to make a single OR gate but there are circumstances where this becomes a necessity and hence this implementation is used.
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